
// Library name: Variation
// Cell name: inverter
// View name: schematic
subckt inverter in out vdd vss
    M0 (out in vss vss) NMOS_VTL w=wn_inverter l=ln_inverter as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M1 (out in vdd vdd) PMOS_VTL w=wp_inverter l=lp_inverter as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends inverter
// End of subcircuit definition.

// Library name: HW4
// Cell name: Latch
// View name: schematic
subckt Latch clk d q vdd vss
    M12 (net10 net17 vss vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M13 (q net10 vss vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M10 (q net22 net17 vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M1 (d clk net17 vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M0 (net22 clk vss vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M11 (net10 net17 vdd vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M14 (q net10 vdd vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M7 (q clk net17 vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M6 (d net22 net17 vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M5 (net22 clk vdd vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends Latch
// End of subcircuit definition.

// Library name: Variation
// Cell name: flip_flop
// View name: schematic
subckt flip_flop clk d q vdd vss
    I3 (clk net14 q vdd vss) Latch
    I2 (net6 d net14 vdd vss) Latch
    M0 (net6 clk vss vss) NMOS_VTL w=wn_latch l=ln_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M1 (net6 clk vdd vdd) PMOS_VTL w=wp_latch l=lp_latch as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends flip_flop
// End of subcircuit definition.

// Library name: Variation
// Cell name: mux
// View name: schematic
subckt mux a b control out vdd vss
    M17 (net051 net066 vdd vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M7 (a control net066 vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M19 (out net051 vdd vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M1 (b net59 net066 vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M0 (net59 control vdd vdd) PMOS_VTL w=wp_mux l=lp_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M16 (net051 net066 vss vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M6 (b control net066 vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M5 (net59 control vss vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M18 (out net051 vss vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
    M10 (a net59 net066 vss) NMOS_VTL w=wn_mux l=ln_mux as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
ends mux
// End of subcircuit definition.

// Library name: Variation
// Cell name: test_circuit_original
// View name: schematic
I10 (net15 freq1 net42 net123) inverter
I9 (net19 net15 net42 net123) inverter
I8 (net23 net19 net42 net123) inverter
I7 (net27 net23 net42 net123) inverter
I6 (net31 net27 net42 net123) inverter
I5 (net35 net31 net42 net123) inverter
I4 (net39 net35 net42 net123) inverter
I3 (net43 net39 net42 net123) inverter
I2 (net47 net43 net42 net123) inverter
I1 (net51 net47 net42 net123) inverter
I0 (freq1 net51 net42 net123) inverter
I21 (clk net61 scan_out vdd gnd) flip_flop
I20 (clk net66 net61 vdd gnd) flip_flop
I19 (clk net71 net66 vdd gnd) flip_flop
I18 (clk net76 net71 vdd gnd) flip_flop
I17 (clk net81 net76 vdd gnd) flip_flop
I16 (clk net86 net81 vdd gnd) flip_flop
I15 (clk net91 net86 vdd gnd) flip_flop
I14 (clk net96 net91 vdd gnd) flip_flop
I13 (clk net101 net96 vdd gnd) flip_flop
I12 (clk net106 net101 vdd gnd) flip_flop
I11 (clk net117 net106 vdd gnd) flip_flop
I22 (scan_out scan_in scan_en net117 vdd gnd) mux
M21 (gnd scan_out net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M20 (gnd net61 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M19 (gnd net66 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M18 (gnd net71 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M17 (gnd net76 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M16 (gnd net81 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M15 (gnd net86 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M14 (gnd net91 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M13 (gnd net96 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M12 (gnd net101 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M11 (gnd net106 net123 gnd) NMOS_VTL w=wn_test l=ln_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M10 (net42 net0291 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M9 (net42 net0293 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M8 (net42 net0295 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M7 (net42 net0297 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M6 (net42 net0299 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M5 (net42 net0301 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M4 (net42 net0303 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M3 (net42 net0305 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M2 (net42 net0307 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M1 (net42 net0309 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
M0 (net42 net0311 vdd vdd) PMOS_VTL w=wp_test l=lp_test as=9.45e-15 \
        ad=9.45e-15 ps=300n pd=300n ld=105n ls=105n m=1
V10 (net0291 scan_out) vsource dc=-49.5m type=dc
V9 (net0293 net61) vsource dc=-45m type=dc
V8 (net0295 net66) vsource dc=-40.5m type=dc
V7 (net0297 net71) vsource dc=-36m type=dc
V6 (net0299 net76) vsource dc=-31.5m type=dc
V5 (net0301 net81) vsource dc=-27m type=dc
V4 (net0303 net86) vsource dc=-22.5m type=dc
V3 (net0305 net91) vsource dc=-18m type=dc
V2 (net0307 net96) vsource dc=-13.5m type=dc
V0 (net0311 net106) vsource dc=-4.5m type=dc
V1 (net0309 net101) vsource dc=-9m type=dc
C0 (net123 gnd) capacitor c=900f
C1 (net42 gnd) capacitor c=900f
